In present Shared Virtual Array (SVA) systems, the centralized shared memory is located on a circuit card separate from the circuit cards where the multiple processors are located. This creates a bottleneck which limits total system performance in two ways. First, the transport latency of getting a memory operation from a processor card to the shared memory card, and then getting the results back, limits the total number of operations that can be done in any given unit of time. Second, since the shared memory operations for all of the processors are single threaded through the memory, the bandwidth of the memory limits the total number of memory operations available to all of the processors. Further, the bandwidth of shared memory operations available to any given processor is limited to the memory bandwidth divided by the total number of processors.
These centralized shared memory bottleneck problems can be solved by providing each processor with its own local copy of the shared memory. This greatly reduces the latency problem because the memory can be physically placed much closer to the processor and run at much higher clock rates. Such a distributed shared memory also improves the shared memory bandwidth because the memories only have to perform read operations from a single processor instead of from all of the processors.
However, such a distributed shared memory architecture creates a new set of problems that did not exist in the central shared memory architecture. Specifically, with such a distributed shared memory, consistency must be maintained between the multiple copies of the same shared memory image. In that regard, there are two types of consistency that must be maintained if the distributed shared memories are to behave the same as a centralized shared memory. These types of consistency may be referred to as copy consistency and sequential consistency.
Copy consistency means that each individual processor's view of its copy of the shared memory is the same as all of the other processors' views of their respective copies of the shared memory at any and every instant in time. This means that any sequence of write operations done on multiple processors to the same location in the shared memory must produce the same results in all copies of that shared memory location. Sequential consistency means that two sequences of instructions running in parallel, sharing data, must produce the same results in all copies of the shared memory when running on two processors as when running on a single processor with a single memory.
Thus, there is needed an improved system and method for a shared memory. Such a system and method would provide local copies of a shared memory to each of a plurality of processors to overcome the bottleneck problems associated with the centralized shared memory architecture of the prior art, while at the same time maintaining consistency in all copies of the distributed shared memory. In particular, such a system and method for a distributed shared memory would maintain copy consistency by ensuring that each of the plurality of processors performs the same write operations on its local copy of the shared memory in the same order. Such a distributed shared memory system and method would also serialize operations of the multiple processors and maintain sequential consistency, such as by prohibiting a processor from performing a read operation on the shared memory while any prior write operations remain unfinished, thereby guaranteeing that all prior write operations can be seen by all processors. In such a fashion, such a system and method could thereby form the backbone of communications between multiple processors in any product (such as a virtual disk controller), working independently of the transport delay or physical separation of multiple processors and making possible a strongly consistent shared memory across networked computers.